Thanks to the progress in the field of production processes of integrated electronic circuits, electronic components have become smaller, thus allowing the production of substrates including a large number of integrated circuits. It is also possible to produce compact electronic circuits including a large number of components and consequently the density of the connection terminals suitable for coupling the integrated electronic circuits has also drastically increased. The latest generation of devices thus has a large number of terminals or pads to place in contact, which have a small area and are often very close to one another.
The pads commonly used in the building of integrated circuits can have very complex and articulated mechanical structures. A structure for a pad suitable for reducing the risk of delamination and microfractures after high mechanical stresses of the assembly and checking process of the chip is described in US 2002/0179991 A1, which is incorporated by reference. In particular, the quoted document describes a pad having a reinforcement structure under the welding area. The reinforcement structure includes a layer of metal and metallic vias that couple the layer of metal to the lower surface of the upper metal layer.
The materials used for the pads are selected based on the applications of the semi-conductive chip. The increasing need for electronic applications capable of withstanding increasingly high temperatures has required the introduction of new materials for the pads and for the connections between the pads and the circuit elements forming part of the integrated circuit in order to ensure a good electrical connection. Moreover, the materials are selected also based on their mechanical characteristics so as to strengthen the pad itself. In some applications aluminum is thus replaced by materials like, for example, nickel, which has a greater hardness than aluminium.
Furthermore bumps can be created above the pads.
A possible structure for a connection bump is described in U.S. Pat. No. 3,986,255, which is incorporated by reference. This structure, since it is formed in part from magnetic materials, as well as ensuring an electrical connection, is also used to manually or automatically move the chip on a substrate and thus align the bumps of the chip with the contact areas of the substrate. A structure of this kind is, however, complex and thus expensive to make.
After having been formed in the substrate of a wafer, the integrated circuits must be tested so as to be able to identify defective components and, where possible, repair them.
The functionality of each integrated circuit in the substrate is checked by means of suitable probes that make contact with the connection terminals or pads of the integrated circuit itself that must be tested and that in the jargon is called DUT (Device Under Test). During the testing process, an ATE (Automatic Test Equipment) or tester is electrically coupled to the wafer on which the electronic components are formed. The interface between the ATE and the wafer is a probe card, including a PCB (printed circuit board) and a plurality of probes that electrically couple the ATE with the pads of the devices under test. In general, the wafer is arranged on a support called a chuck belonging to an apparatus called a prober.
Since the DUTs include a large number of pads close to one another, the correct alignment of the probes of the probe card with the corresponding pads during the testing step of the integrated circuits is of crucial importance.
FIG. 39 schematically illustrates a testing system for integrated circuits in which an electromagnetic interface is used to ensure the exchange of information between the ATE 1200 and the DUT 1100 through wireless communication based on electromagnetic probes. In these systems the ATE 1200 and the DUT 1100 include suitable transmitting and receiving circuits 1140, 1240 coupled to inductive antennae. The DUT 1100 can be fed inductively through the antennae, or else in the case in which the chip has high power consumption, the power supply can be provided through probes coupled to the pads of the DUT. To check the integrated circuits, “power line” type interfaces can also be used. In this case, a radio frequency signal can be superimposed on the power supply so that the communication between the ATE 1200 and the DUT 1100 occurs through the power line. An example of these systems is described in US 2009/0224784, which is incorporated by reference.
The use of chips suitable for receiving/transmitting wirelessly requires the integration of inductive elements suitable for transmitting signals, for example, in radio frequency, into the substrate of the chip. A problem that must be tackled in producing systems on chips of this kind is the development of cost-effective processes and methods to create inductors and transformers that can be integrated in the substrate of the chip or coupled to it if external.
A way of making inductors and transformers coupled to an integrated circuit is described in US 2008/0029845, which is incorporated by reference and which is schematically illustrated in FIG. 40. The idea is to use the inductance created by the connection wires 1300 or wire bonds that couple the different terminals 1110 on the surface of the chip together. Since the inductance created by the connection wires is typically insufficient to support applications like, for example, power converters, the connection wires can be covered with a magnetic coating 1316, like, for example, ferrite powder suspended in an epoxy resin, on a portion of the connection wire 1300 situated above the plane of the upper surface of the chip.
However, this solution is not very strong given that the inductive elements are arranged outside of the substrate and the magnetic coating can be subject to deterioration, thus causing a deterioration of the performance of the semi-conductor chip. In addition, the design of these inductive structures is greatly limited in the shape, size, and position of the inductive elements themselves, and this is also due to the size and number of chips on the substrate. Moreover, the inductive structures are created from connection wires outside of the chip being based on a wire bonding process, and, therefore, the various structures will have a greater variability of their characteristics than the inductive structures that can be integrated in the chip.
US 2008/0265367, which is incorporated by reference, describes an integrated circuit including an inductive element and that can be magnetically aligned with a rewiring substrate, and such a structure is schematically illustrated in FIG. 41. In particular, the semi-conductive chip 2100 includes an alignment element that consists of an induction coil 2107 and a connection terminal 2108 that consists of a bump created above a pad. The coil 2107 is located below the contact terminals 2108 positioned at the corners of the semi-conductive chip 2100 and the alignment is carried out by inducing a magnetic field in the induction coil. The coil 2107 is arranged in a through hole 2137 of the semi-conductive chip and has a lateral dimension approximately equal to that of the connection terminal at the corner of the semi-conductive chip.
The contact terminal 2108 is, however, a dummy pad because it is located above a through hole 2137 containing the coil 2107 that is not coupled to the pad. Moreover, inside the coil 2107 there are no structures suitable for coupling the connection terminal 2108 to other circuits that are integrated in the chip 2100. The pad is finally coated with a ferromagnetic material that could even not be conductive. Consequently, the pad or corner bump of the semi-conductive chip described above can just be used to facilitate an optical alignment that is conventionally used for the chip itself with another element like, for example, a rewiring substrate, but it is not then used during the operation of the end product given that it is not coupled to the other circuits that are integrated in the chip 2100. Since the connection pads and the inductive elements are generally of substantial size, a substantial portion of the chip 2100 will remain unused during the operation of the chip in the final application, thus having a negative impact upon the size of the end product and on its cost.
Italian patent application TO 08A001014, which is incorporated by reference, describes a chip, illustrated in FIG. 42, including structures that can be coupled to a pad 3111 around which an antenna 3112 is formed. In this type of structure, the presence of the antenna 3112 around the pad 3111 requires the use of a substantial portion of volume of the substrate 3500 around the pad 3111.
A problem of the structure described above is that the inductive elements thus formed occupy a large portion of the substrate, thus causing an increase in the size of the integrated circuit itself with a consequent increase in costs.
Consequently, the structures described in the aforementioned documents belonging to the state of the art either are unsuitable for exchanging information with external apparatuses wirelessly, or else they describe structures with a design that is not very flexible, not very strong, or of substantial size.
In integrated circuits like the one described above, the pad is formed with conductive materials and, therefore, if an inductive element, like for example an antenna, is formed in the immediate vicinity of the pad, the inductor will influence the operation of the pad itself and vice versa. In general, the inductor will have problems working correctly as the operating frequency of the integrated circuit increases, following the eddy currents induced in the conductive material itself. Moreover, the force lines of the magnetic field induced by the inductive element can disturb the circuits adjacent to the inductor. For this reason, in conventional integrated circuits it is common practice to avoid forming the inductive elements in the vicinity of the electric/electronic circuits integrated in the substrate and it is a goal to reduce to the minimum the structures in the pad that could create parasitic inductances.
In the structure described in US 2008/0265367, which is incorporated by reference, and as schematically illustrated in FIG. 41, indeed, the inductive element is situated at the edges of the substrate and coupled to a dummy pad, i.e. that is not electrically coupled to any circuit structure integrated in the substrate. Since the inductive element is not coupled to any integrated circuit element suitable for transmitting, it cannot be used as receiver/transmitter and can, therefore, only be used to align the integrated circuit with a structure outside of it, like for example a rewiring circuit, during the steps of the assembly process of the integrated circuit itself.
The design described above thus needs space to be reserved on the surface and inside the substrate for a structure that can only be used in the production step of the integrated circuit, thus contributing to drastically increasing the size of the integrated circuit and its cost.